In digital logic design, engineers often use pre-defined standard cells pulled from an electronic library (or database) in order to avoid constantly redesigning often used elements. These standard cells contain layouts for many logic functions and logic gates that have been carefully designed and optimized for various applications. Commonly used cells have multiple variations, including, for example, a standard cell that has been modified for maximum speed (most likely at the expense of some other circuit characteristic, such as power consumption), for minimum power consumption (again at the expense of some other characteristic), and so forth. These modified standard cells allow circuit designers more options and flexibility in creating digital circuits while still avoiding the costly procedure of redesigning cells.
Ideally, a digital logic design runs at a very high speed but consumes very little power (thereby producing very little heat). Usually, however, the faster a particular element in a design runs, the more power it consumes. Engineers must thus decide whether they want to sacrifice speed for power, or power for speed. One method commonly employed to increase propagation speeds of individual devices logic elements on a critical path (a path that needs to be optimized for speed) is to lower the threshold voltage (or, in other words, the turn-on voltage) of devices within those logic elements on the critical path (the path that needs to be optimized for speed) in a digital design. While this technique increases the switching speed of the individual devices in the logic element (thereby reducing the delay introduced into the critical path by those devices), the low threshold device consumes much more power due to the devices turning on earlier as well as the current leakage when the devices are off.
One prior art solution is to simply implement a standard cell library with non-mixed threshold voltage cells and mixed threshold voltage cells (i.e. at the transistor level) having footprints no larger than the non-mixed cells, wherein an implant overlay of oxide thickness and space between first and second threshold voltage devices match a minimum contacted space. This solution, however, fails to account for a method of intelligently selecting when to use non-mixed and when to use mixed cells in a design.